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ics9db102 idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 2 output pci express* buffer with clkreq# function datasheet 1 spread compatible pll control logic smbdat smbclk clk_int c l k _ i n c pll_bw iref pciex0 pciex1 clkreq1# clkreq0# description output features 1-to-2 zero-delay or fanout buffer for pci express.the ics9db102 zero-delay buffer supports pci express clocking requirements. the ics9db102 is driven by a differential src output pair from an ics ck409/ck410-compliant main clock generator such as the ics952601 or ics954101. it attenuates jitter on the input clock and has a selectable pll band width to maximize performance in systems with or without spread- spectrum clocking. 2 - 0.7v current mode differential output pairs (hscl) funtional block diagram key specifications cycle-to-cycle jitter < 35ps output-to-output skew < 25ps features/benefits clkreq# pin for outputs 1 and 4/output enable for express card applications pll or bypass mode/pll can dejitter incoming clock selectable pll bandwidth/minimizes jitter peaking in downstream pll?s spread spectrum compatible/tracks spreading input clock for low emi smbus interface/unused outputs can be disabled
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 2 pin configuration pll_bw 1 20 vdda clk_int 2 19 gnda clk_inc 3 18 iref **clkreq0# 417**clkreq1# vdd 516 vdd gnd 6 15 gnd pciext0 714 pciext1 pciexc0 813 pciexc1 vdd 912vdd smbdat 10 11 smbcl k ics9db102 note: pins preceeded by '**' have internal 120k ohm pull down resistors 20-pin ssop & tssop vdd gnd 5,9,12,16 6,15 pci express outputs 96 smbus 20 19 iref 20 19 analog vdd & gnd for pll core description pin number power groups pin description pin # pin name pin type description 1 pll_bw input 3.3v input for selecting pll band width 0 = low, 1= high 2 clk_int input "true" reference clock input. 3 clk_inc input "complementary" reference clock input. 4 **clkreq0# input output enable for src/pci express output pair '0' 0 = enabled, 1 = tri-stated 5 vdd power power supply, nominal 3.3v 6 gnd power ground pin. 7 pciext0 output true clock of differential pci_express pair. 8 pciexc0 output complement clock of differential pci_express pair. 9 vdd power power supply, nominal 3.3v 10 smbdat i/o data pin of smbus circuitry, 5v tolerant 11 smbclk input clock pin of smbus circuitry, 5v tolerant 12 vdd power power supply, nominal 3.3v 13 pciexc1 output complement clock of differential pci_express pair. 14 pciext1 output true clock of differential pci_express pair. 15 gnd power ground pin. 16 vdd power power supply, nominal 3.3v 17 **clkreq1# input output enable for src/pci express output pair '1' 0 = enabled, 1 = tri-stated 18 iref output this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 19 gnda power ground pin for the pll core. 20 vdda power 3.3v power for the pll core. pins preceeded by '**' have internal 120k ohm pull down resistors note:
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 3 absolute max electrical characteristics - input/supply/common output parameters symbol parameter min max units vdda 3.3v core supply voltage v dd + 0.5v v vdd 3.3v output supply voltage gnd - 0.5 v dd + 0.5v v ts storage temperature -65 150 c tambient ambient operating temp 0 70 c tcase case temperature 115 c esd prot i nput esd protect i on human body model 2000 v t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v1 input low voltage v il 3.3 v +/-5% v ss - 0.3 0.8 v 1 input high current i ih v in = v dd -5 5 ua 1 i il1 v in = 0 v; inputs with no pull-up resistors -5 ua 1 i il2 v in = 0 v; inputs with pull-up resistors -200 ua 1 full active, c l = full load; 75 100 ma 1 all differential p airs tri-stated 27 50 ma 1 in p ut fre q uenc y 3 f i v dd = 3.3 v 99 100 101 mhz 1 pin inductance 1 l pin 7nh1 c in logic inputs 5 pf 1 c out output pin capacitance 4.5 pf 1 clk stabilization 1,2 t stab from v dd power-up to 1st clock 1.8 ms 1 modulation fre q uenc y trian g ular modulation 30 33 khz 1 spread spectrum modulation fre q uenc y f mod lexmark modulation 25 45 khz 1 smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v olsmbus @ i pullup 0.4 v 1 current sinking at v ol = 0.4 v i pullup smbus sdata pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. input low current input capacitance 1 operating supply current i dd3.3op
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 4 electrical characteristics - pciex 0.7v current mode differential pair t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , ref = 475 ? parameter symbol conditions min typ max units notes current source output im p edance zo v o = v x 3000 ? 1 volta g e hi g hvhi g h 660 850 1,3 volta g e low vlow -150 150 1,3 max volta g e vovs 1150 1,3 min volta g e vuds -300 1,3 crossing voltage (abs) vcross(abs) 250 350 550 mv 1,3 crossing voltage (var) d-vcross variation of crossing over all ed g es 12 140 mv 1,3 lon g accurac y pp m see t p eriod min-max values 0 pp m1,2 100.00mhz nominal 9.9970 10.0030 ns 2 100.00mhz s p read 9.9970 10.0533 ns 2 absolute min p eriod tabsmin 100.00mhz nominal/s p read 9.8720 ns 1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 30 125 ps 1 fall time variation d-t f 30 125 ps 1 t p d pll mode. 135 185 ps 1 t p db yp bypass mode 3.2 3.7 ns 1 duty cycle d t3 measurement from differential wavefrom 45 55 % 1 output-to-output skew t sk3 v t = 50% 25 ps 1 t jcyc-cyc pll mode. measurement from differential wavefrom 35 ps 1 t jcyc-cycbyp additve jitter in bypass mode 30 ps 1 1 guaranteed b y desi g n, not 100% tested in p roduction. . 3 i ref = v dd /(3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 2 all long term accuracy and clock period specifications are guaranteed with the assumption that the input clock complies with ck409/ck410 accuracy requirements input to output delay jitter, cycle to cycle mv measurement on single ended signal using absolute value. mv average period tperiod statistical measurement on single ended signal using oscilloscope
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 5 electrical characteristics - pll parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% grou p parameter descri p tion min t yp max units notes pll jitter peaking j peak-hibw (pll_bw = 1) 0 1 2.5 db 1,4 pll jitter peaking j peak-lobw (pll_bw = 0) 0 1 2 db 1,4 pll bandwidth pll hi b w (pll_bw = 1) 2 2.5 3 mhz 1,5 pll bandwidth pll lobw (pll_bw = 0) 0.4 0.5 1 mhz 1,5 pcie gen 1 phase jitter (1.5 - 22 mhz) 40 108 ps 1,2,3 pcie gen 2 jitter (8-16 mhz, 5-16 mhz) hi-band >1.5mhz (pll_bw=1) 2.7 3.1 ps rms 1,2,3 pcie gen 2 jitter (8-16 mhz, 5-16 mhz) hi-band >1.5mhz (pll_bw=0) 2.2 3.1 ps rms 1,2,3 pcie gen 2 jitter (8-16 mhz, 5-16 mhz) lo-band <1.5mhz 1.3 3 ps rms 1,2,3 notes: 1. guaranteed by design and characterization, not 100% tested in production. 2. see http://www.pcisig.com for complete specs 3. device driven by 932s421bglf or equivalent 4. measured as maximum pass band gain. at f requencies w ithin the loop bw, highest point of magnif ication is called pll jitter pea king. 5. measured at 3 db dow n or half pow er point. jitter, phase t jphasepll
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 6 src reference clock common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50 ohm trace. 0.5 max inch 1 l2 length, route as non-coupled 50 ohm trace. 0.2 max inch 1 l3 length, route as non-coupled 50 ohm trace. 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 1 l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 1 differential routing to pci express connector dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch 2 figure 1 down device routing. rs rs rt rt hscl output buffer pci ex board down device ref_clk input l1 l2 l3? l4 l1? l2 l3 l4? figure 1 figure 2 pci express connector routing. rs rs rt rt hscl output buffer pci ex add in board ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? figure 2
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 7 alternative termination for lvds and other common differential signals. figure 3. vdiff vp-p vcm r1 r2 r3 r4 note 0.45 v 0.22v 1.08 33 150 100 100 0.58 0.28 0.3 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 cable connected ac coupled application, figure 4 component value note r5a,r5b 5% r6a,r6b cc 0.1 0.350 vcm volts figure_3. r1b r1a r2a r2b hscl output buffer down device ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? r3 r4 figure_4. pcie device ref_clk input l4 l4? r6b r5b r6a r5a 3.3 volts cc cc 8.2k 5% uf 1k
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 8 general smbus serial interface information for the ics9db102 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d4 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d4 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d5 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack pstop bit x byte index block write operation slave address d4 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d5 (h) index block read operation slave address d4 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 9 smbus table: device control register, read/write addr ess (d4/d5) pin # name control function t yp e0 1pwd bit 7 sw_en enables smbus control rw functions controlled by smbus re g isters functions controlled b y device p ins 1 bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 pll bw #adjust selects pll bandwidth rw low bw high bw 1 bit 0 pll enable bypasses pll for board test rw pll bypassed (fan out mode) pll enabled (zdb mode) 1 smbus table: output enable register pin # name control function t yp e0 1pwd bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x smbus table: function select register pin # name control function t yp e0 1pwd bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x reserved - reserved - - - - - - - - - - b y te 2 reserved - - - b y te 1 - - - - - - reserved - - - reserved - - reserved - b y te 0 - - reserved reserved - - reserved - reserved - - reserved reserved - reserved - reserved - - reserved - reserved reserved - reserved - reserved - - reserved - reserved
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 10 smbus table: vendor & revision id register pin # name control function t yp e0 1pw d bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 0 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function t yp e0 1pw d bit 7 r 0 bit 6 r 0 bit 5 r 0 bit 4 r 0 bit 3 r 0 bit 2 r 1 bit 1 r 1 bit 0 r 0 smbus table: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 0 device id = 06 hex - - - - b y te 3 - revision id - - - - - vendor id - - - - - - - b y te 4 - - - byte 5 - writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. - - - - - - - - - - -
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 11 ordering information ics 9db102 y flft example: designation for tape and reel packaging lead free, rohs compliant package type f = ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) ics xxxx y f lf t min max min max a 1.35 1.75 .053 .069 a1 0.10 0.25 .004 .010 a2 -- 1.50 -- .059 b 0.20 0.30 .008 .012 c 0.18 0.25 .007 .010 d e 5.80 6.20 .228 .244 e1 3.80 4.00 .150 .157 e l 0.40 1.27 .016 .050 n a 0808 zd in millimeters in inches common dimensions see variations 0.635 basic 0.025 basic common dimensions 20-lead, 150 mil ssop ( qsop ) see variations see variations see variations see variations symbol see variations
idt tm /ics tm 2 output express* buffer with clkreq# function ics9db102 rev f 08/06/07 ics9db102 2 output pci express* buffer with clkreq# function 12 ordering information ics 9db102 y glft example: index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a 0808 aaa -- 0.10 -- .004 variations min max min max 20 6.40 6.60 .252 .260 10-0035 20-lead, 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) designation for tape and reel packaging lead free, rohs compliant package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 to 7 digit numbers) ics xxxx y g lf t
ics9db102 2 output pci express* buffer with clkreq# function innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # f 08/06/07 1. added phase noise parameters, updated input to output delay values. 2. pll bw moved to pll parameters table. 3. added terminations tables. various

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